Building an SRAM Substitute
How would you use modern RAM and interface logic to replace 8 MB of vintage SRAM? A cheap and simple solution would make a big difference for many retrocomputing and hobby electronics projects. This question arose from a discussion at 68kmla.org, from a project to design an 8 MB RAM expansion card for the 1989 Macintosh Portable, and it piqued my interest. Modern components are so much cheaper and more capable than their 1980’s equivalents, there must be a way.
As you might remember from long-ago engineering classes, standard computer RAM comes in two basic types: static RAM (SRAM) and dynamic RAM (DRAM). SRAM is very convenient and easy to use. The CPU places an address on the SRAM’s address pins, and some short time later the CPU can read the value stored at that address from the SRAM’s data pins. Once stored, values remain in SRAM for as long as the power is kept on. DRAM usage is more complex. The CPU places half of the address bits on the DRAM’s address pins (the row address), then a short time later it removes these and places the other half of the address bits on the DRAM’s address pins (the column address), and only then can it read the value stored at that address. The stored values are not persistent, but will be lost after a few milliseconds unless they are constantly refreshed.
For retro/hobby projects, SRAM is ideal because there’s no memory controller or refresh logic required. The Mac Portable RAM expansion card also uses SRAM, because that’s what the Portable was designed to use – perhaps to save power that would otherwise be lost to refresh cycles while the computer was asleep.
The problem is that in 2015, SRAM is rarely used anymore. The RAM in your new Windows or OSX machine is all some flavor of DRAM. A search of popular online electronics vendors like Digi-Key, Mouser, and Farnell reveals that few SRAM chips are available for sale today, and the ones that are available are low capacity and expensive. For the Mac Portable 8 MB RAM expansion card, the most likely candidate is this 2 MB Alliance Memory SRAM chip – so four chips would be required. But that chip is $10 each! You’d have $40 in RAM costs before even considering the cost of the other components, the PCB, and assembly. $40 for 8 MB of RAM seems crazy, when you can buy 8 GB of modern RAM for about the same price.
Building a Frankenstein RAM
Can some flavor of modern DRAM be used, along with some interface glue logic, to make an 8 MB RAM card that looks like SRAM to the Mac Portable? In theory, I believe it’s possible, but the details look tricky. The SRAM speed is 55 ns, meaning the CPU must wait 55 ns after presenting the address before it can read the value stored there. The proposed SRAM replacement would need a state machine of some kind that could latch the address, break it into separate row and column addresses, present these to the DRAM, and then grab the stored value and provide it to the CPU, and then do a DRAM refresh cycle, all in less than 55 ns. That’s something like 5 operations, so each one would need to take less than 11 ns, implying a 91 MHz clock rate for the state machine. This state machine would also need to handle any necessary DRAM initialization (CAS latency setting?), and things like burst mode and other DRAM details that I’ve heard of but don’t really know what they are. It could be implemented in a CPLD or FPGA. It would likely require a large number of pins, perhaps 60 or more, for the address and data busses on both sides. That probably rules out most CPLDs, and requires a higher pin count FPGA.
Here’s one candidate chip: an 8 MB Alliance Memory SDRAM that’s just $1.53. The price is certainly right. It looks like it would be fast enough, given my quick peek at the data sheet. But the complexity of building that FPGA memory controller interface is a bit daunting.
How about using some kind of modern synchronous SRAM, instead of DRAM? I’ve never really looked at synchronous SRAM, though I assume from its name it’s like standard SRAM with the addition of a clock for the control signals. But a quick glance at Digi-Key shows that it’s no cheaper than old-school SRAM.
What about using Flash RAM? That’s probably no good – it’s not designed to be constantly modified like a general purpose RAM, and would likely fail after some tens or hundreds of thousands of update cycles. And I’m not certain it would be fast enough, either. Flash is normally a page-centric memory, so in order to modify one memory location, an entire page must be erased and re-written. But it sure is cheap!
Maybe a fast microcontroller could be used instead of an FPGA to implement the memory controller interface. Some of the newer ARM microcontrollers have a built-in DRAM controller, and can run at 100s of MHz. Would it be crazy to consider writing a 10 line program that sits in a tight loop, watching the CPU address and data bus on one set of pins, and fetching/storing data to DRAM on another set of pins?
Other bright ideas?
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I think an FPGA would increase the price (and complexity) too much, but a CPLD may be cheap enough. I’m pretty sure that any solution would require a bodge wire to get access to the system clock, so that refreshes could happen in phase with instruction processing.
On the Commodore 64, the sneaky engineers made the video chip(VIC) act as a dram refresh controller. It would also provide the clock for the actual CPU to ensure it wasn’t doing refresh while the CPU was trying to access dram. Unfortunately it’s hard to “add” that on to an existing design.
Look forward to seeing other comments.
https://en.wikipedia.org/wiki/EDRAM
Looks like there’s some “pseudo static RAM” at around the $5 mark for 8MB. See http://www.mouser.com/Semiconductors/Memory/SRAM/_/N-4bzpt?P=1z0vzw7. Unfortunately, it’s all BGA, as it was designed as SRAM-replacements in cell phone designs.
It looks like a small device could be made with the above mentioned pseudo static RAM, a level shifter and a 3.3v LDO to make a 5v-tolerant 8MiB device.
Thoughts?
Level shifter:
http://www.ti.com/lit/ds/symlink/sn74cb3t16210.pdf
Pseudo SRAM:
http://www.mouser.com/ds/2/198/66WVE4M16BLL-258704.pdf
LDO:
http://www.ti.com/product/TPS730/datasheet
The Mac Portable is already 3.3V, so no level shifting is needed. BGA would be an issue though. Unless it’s possible to hand solder initial prototypes for testing, I’m not sure it would be possible to design a working board.
What form factor would be useful?
It seems like it would be possible to make a TSOP-48 compatible form factor using castellated vias.
Anything with externally accessible pins would be better – TSOP would work. Maybe a hand-assembled board with a BGA chip would be possible, using a stencil, solder paste, and a toaster oven reflow or hot air gun. I’d be quite nervous, though – how could you ever know if all the pads were soldered properly? Alternatively, maybe a prototyping service with the proper equipment could assemble a protoype board, but that would probably be pretty expensive as a one-off for just a single board. I’ve always viewed BGA components as the unobtanium of electronics hobbyists, but maybe I’m too conservative.
A friend once told me that the biggest hurdle to using BGAs is summoning the hubris to actually think that you can do it.
I’d be game to throw together a quick design and hand assemble a few boards for people to test. Which package would be better to emulate, SOP28 or TSOP28?
No, the mac portable is 5V logic. I designed the 8MB RAM card to level-shift to 3.3V for both the CPLD and the 8MB of SRAM thats on the card. It worked fine. Using a jelly-bean 1117 regulator.
BTW i have pulled, remounted, and mounted new countless BGAs. but it does take good equipment to do it. I have done it with a hotplate before, or on the cheap a stove skillet and hot air gun. Not fun, but i have done it.
love in the 8mb bga solution, do it steve!! 🙂
sounds simple!
maybe can be used for other solutions as well!!!! other then just portable.
check out this amiga hacking blog:
http://amigaprj.blogspot.com/2013/05/amiga-fast-ram-expander-with-simm.html
http://amigaprj.blogspot.com/2014/09/8-mb-fast-ram-expander-cpld-version.html
afair this realizes linear address to row/column translation + refreshing
I believe that some of the bigger microcontrollers have built in SDRAM controllers. Some of the STM32F4 range seem to.
Perhaps if your memory didn’t need to be too fast you could use one of those to connect to the ram and provide a slower static memory-like interface to whatever needs it?
Not sure of the interface requirements, but this looks promising – 8MB 55ns asynchronous SRAM for ~$6:
http://www.digikey.com/product-detail/en/AS6C8008A-45ZIN/1450-1189-5-ND/4499097
It is 8Mbit not 8Mbyte.
While BGA is not insurmountable, it definitely is trickier for prototyping. What about this? http://www.digikey.com/product-detail/en/issi-integrated-silicon-solution-inc/IS66WV51216EBLL-55TLI/706-1427-5-ND/5320130