Fixed Size Instructions
I’ve finished my experiment with fixed-size instructions for Tiny CPU, and the results are encouraging. I did a straightforward conversion to a 16-bit instruction size, with the opcode in the upper 6 bits and the address (if any) in the lower 10. Here’s how it compares to the original, variable-size instruction version:
| Variable Size | Fixed Size | Percent Reduction | |
|---|---|---|---|
| macrocells | 119 | 112 | 6 |
| verification program size (bytes) | 2055 | 1890 | 8 |
| verification program execution time (clocks) | 835 | 574 | 31 |
So it’s an improvement across the board. The only drawback is that increasing the address size to something larger than 10 would be fairly difficult. It’s technically possible to fit all the opcodes into 5 bits (there are 31 unique opcodes), allowing for 11 bits of address. However, it would be a poor encoding that would probably require the decoding logic to be substantially more complex, increasing the macrocell count.
I wrote a tool to convert variable-sized program binaries into fixed-size, but it’s ugly and brittle. My next step, therefore, will be to write a custom Tiny Assembler for my Tiny CPU.
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Dude, you still amaze me.
Is your Tiny CPU still Von Neumann or is it now Harvard? Is the instruction loaded one byte at a time, or do you expect to use a 16-bit wide bus for each instruction? I’m curious to know where your savings came from.
I wouldn’t worry about only having 10 bits of address. If you need more memory, you could do some cheap banking scheme (in or outside the the CPLD). Not nice, but a common hack.
It is still Von Neumann, and it loads the instructions one byte at a time over the 8-bit bus.
With the old design, all jump, branch, and call instructions were three bytes, and took (at least) three clocks. Now they are two bytes and (for jump and branch) two clocks. Some single-byte instructions grew to two bytes, though, so in the end the size change was almost net neutral. Single byte instructions still took two clocks in the old design, because of limitations of that design, so increasing their size doesn’t actually make them any slower.
Switching to fixed-size instructions also helped substantially simplify the control state machine, reducing it from 20 states to 12. That’s where most of the macrocell savings came from.
Good idea about banking.
After further thought, I realized that my analysis of fixed-size instructions was one of the dumber things I’ve said recently. The size and speed advantages of the modified CPU all come from shrinking the address space from 16 to 10 bits, with the consequent reduction in instruction size for many instructions. It has nothing to do with the instructions having a fixed width.
In fact, the fixed width actually makes size and speed worse for instructions that do not require an address. The best size and speed results should be achieved by combining two-bytes instructions (with 10 bit addresses) with one-byte instructions (with no address). This would require somewhat more complex control logic, however.