Xilinx vs. Altera Tools For Hobbyists
I used to believe that Altera’s FPGA tools were much more hobbyist-friendly than the comparable Xilinx tools, and I frequently bashed the Xilinx tools whenever the topic came up. But after giving them a head-to-head comparison recently, I think I may have to eat my words. The truth is they’re both pretty rough and clunky, and difficult for a beginner to get the hang of, but the Xilinx tools are definitely superior in some important areas.
My FPGA apprenticeship started out poorly with Xilinx in 2009. Over the couple of years I’ve owned a Xilinx Spartan 3A FPGA starter kit, I’ve learned to really hate it and the confusing Xilinx tools and documentation. Trying to get the DDR2 DRAM working on the Xilinx board was an exercise in futility that occupied several months of my time, and I eventually just gave up, as I couldn’t even get the reference design to work. The Spartan 3A starter kit hardware also seems needlessly complex, like they threw one of every possible component on there just to serve as an example. That makes it a confusing mass of jumpers, options, and shared pins that obscures whatever you’re trying to create. Too often I also found the Xilinx documentation and examples incomprehensible, and their online support poor to none. Eventually I gave up on them, and vowed to only use parts from their competitor Altera in the future.
A year or so later, the opportunity to try Altera hardware and tools came, during the development of Tiny CPU. It was a mostly positive experience, although I didn’t really attempt anything very complex. When I needed it, I found the Altera documentation to be decent, and the project went forward without ever hitting any Altera-specific snags. I viewed the result as promising, but not really conclusively better than Xilinx.
During the recent development of Plus Too, I’ve finally had an opportunity to try both Xilinx and Altera tools for the same project, and make a direct comparison. I first spent about a week gettings things set up on the Xilinx board, which culminated in the “Sad Mac” I wrote about yesterday. Then for the past two days, I’ve been translating the existing design to get it working on the Altera board. I love the Altera DE1 hardware– it’s uncluttered, has SRAM *and* SDRAM, and comes with a nice program that can be used to interactively control the hardware or read/write the on-board memory. When it comes to the tools, however, moving from Xilinx to Altera definitely felt like taking a step backward.
Windows 3.1 called. It wants its interface back.
My first complaint about the Altera tools is the interface, which is a UI gem straight out of 1993. Yes I know it’s a petty complaint, but it reinforces the feeling of cruftiness that permeates everything else in the Altera tools. Check out a couple of screen shots:
Those message tabs remind me of MSVC 6.0. And the navbar icons use about nine unique colors across the whole set. And what’s with the balloon help menu?
Here are the corresponding sections of the Xilinx interface for comparison:
That feature is not licensed and has been disabled
Another gripe about the Altera tools is that so many features have been locked out of the free edition. I understand they need to hold something back for the professional edition of their tool, but some of the things they lock just seem petty. After a full compilation run, the output window will be full of warnings about all these tantalizing features you’re not getting. For example if you synthesize your Altera model on a computer with a multi-core CPU (pretty much any CPU these days), you’ll get this warning:
WARNING: Parallel compilation is not licensed and has been disabled
Thanks for nothing, Altera. The Xilinx tools happily spins off multiple threads for each of my CPU cores, and tells me it’s doing it too.
What simulation?
An essential part of FPGA development is simulating the design, because it’s generally much easier to find mistakes in simulation than in the real hardware. You can view every waveform, step through time, set breakpoints, and other sorts of things like you’d do in a functional programming language like C. With the Xilinx tools, I was able to simulate the Plus Too design by switching to the Simulation view, and double-clicking Simulate Behavioral Model. The built-in simulation tool ISim started right up, and within moments I was debugging the design, watching the simulated CPU talk to simulated RAM, ROM, and video. Professionals might need something more powerful than ISim, but it was great for my needs.
The Altera simulation experience was a nightmare in comparison. It took me some time to realize that the Altera Quartus II software doesn’t include any built-in simulator, so I wasted quite a while assuming I was doing something wrong when simulation didn’t work. Altera recommends that you use Modelsim Altera Edition, which is a separate product that must be downloaded and installed separately. Once that’s done, you need to go back into the Altera software and tell it to use Modelsim as the simulation tool, which involved more poking around in menus that are doubtless familiar to pros but took me a while to discover.
Once I had Modelsim AE launching with my design, I thought I was home free. Instead, I was greeted by a laundry list of errors like “Unresolved defparam reference to ‘altpll_component’ in altpll_component.port_extclk3.” After some more swearing and poking around, I found that Modelsim was relying on some environment variables that weren’t set. Environment variables… OK. I made the necessary environment settings, but it still didn’t work. It seemed that Modelsim was unable to parse the definitions for any Altera megafunctions (their IP blocks). A few hours of Googling for answers didn’t find any obvious solutions. It seemed that it might somehow be related to instantiating megafunctions with VHDL implementations from inside a Verilog file, but all my megafunctions were created by the Altera wizard, so they should be fine right? Wrong. Eventually I hand-edited the modelsim.ini file to force it to use Verilog implementations of the megafunctions instead of VHDL ones, and that worked. There was probably some simpler way to do it, but I never found it.
You got your VHDL in my Verilog
Once the simulation model finally compiled successfully, I was ready to start debugging, only to be met with the error message “ALTERA version supports only a single HDL”. Huh? The translation is “you can’t simulate designs containing both Verilog and VHDL files unless you buy the commercial version of ModelSim for over a thousand dollars”. Since my design files are Verilog, but the TG68 68000 core is VHDL, that meant I was dead in the water. In contrast, Xilinx’s ISim simulated all this with ease and no complaints.
It’s the software, stupid
For most of us electronics hobbyists who are interested in FPGAs, the choice of what device or board to use isn’t really determined by which has the most 18-bit multipliers or other whiz-bang features. It’s not really determined by the cost, either, since generally we’re only buying one device. Instead, it’s determined by how easy the device is to use, and how quickly we can accomplish our goals with the hardware. The best software tools are like a trusty set of wrenches that let us quickly open things up and tinker with them, focuing our attention on the novel parts of the project. Poor tools force you to spend time thinking about them instead of your project, and I wish there were better FPGA tools options for hobbyists. From the two major FPGA vendors, my nod goes to the Xilinx tools if you care strongly about simulation.
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If FPGAs were easy to use… I’d be paid much less.
You’re definitely right that the tools are not hobbyist-friendly, or even professional-friendly. They’re just fiendly.
If you’re more comfortable with command line development, you could xtclsh and build/simulate your design from there (If you like a retro TCL shell that looks like it was developed a decade or two ago).
Here’s a silly idea: an alternative GUI that wraps the Altera or Xilinx command-line tools, and provides a simplified, more familiar interface. I would model it on the Microsoft Visual Studio IDE, or other familiar C/Java IDE. A few things I would do:
1. Eliminate the lower-left “process” pane that’s common to both Xilinx and Altera’s tools. There should just be a file/hierarchy view on the left, and menu/toolbar options to “Build Project” (synthesis and map/route/place), “Debug” (launches the simulator), and “Program Device” (creates programming file and writes the bitstream to the FPGA).
2. Filter out all the useless warning/error messages about disabled features and other stuff that most people will rarely care about.
3. Substitute more comprehensible warning/error messages for some of the more common, difficult to understand messages. Include a link to built in help with a more detailed explanation.
4. Combine and relocate all the settings and preferences into two places: IDE settings, and project settings.
5. Integrate simulation as tightly as possible, using terminology and an interface similar to running a .exe in an integrated debugger.
6. Eliminate all the other toolbar/menu options for features you can’t actually use in the free versions of the tools. Why have a button that just says “you’re not allowed to use this feature” when you click it?
7. If you have top-level signals not assigned to any specific FPGA pins, it should be treated as an error. Integrate the pin placement editor into the project settings. Separate the pin placement config from other less common per-pin options like signal format and slew rate.
The FPGA vendor tools have always been hard to use. It seems like they thought of the tools as almost an after thought. This has created a few 3rd party companies that created alternate synthesis tools, but I’m not sure how much of that has caught on – even these are “professional”, meaning they cost thousands of dollars.
I like your wrapper GUI idea. One thing that Modelsim and probably isim lack is a good environment for debugging a soft processor. I’ve been working on a soft processor and have gotten to the point of writing code for it. It would be nice to have a debugger that would do breakpoints, stack trace, register dump, etc. instead of having to look at all these as signals at the hardware simulation level.
I’ve gotten to where I only use the ISE IDE to create an initial project and then use command line tools after that to do builds. I run simulations the same way – a Modelsim script and then just open the resultant waveform file in Modelsim once the simulation completes. But this was on large Virtex-5 FPGA designs that take 2 hours to build and 30 minutes to sim a few microseconds.
You’ve made something wrong with Modelsim-AE. I’ve installed it just after Quartus install and it worked just right there. No problems about Altera Megacores or other stuff.
Yes, I very likely did do something wrong with the Modelsim-AE install. You were simulating a design written in Verilog, that used Altera megacores like the PLL clock synthesizer? Is there some configuration option that I missed?
If you think that getting ram to work on the 3A is hard…… they you better not try the XUP2, says it works with up to 2GB of ram, it barely holds together with 512Mb
Bought the XUP2 for my dissertation work……. 5 months later it was a discontinued product then dropped from the latest version of the Xilinx toolset.
All these FPGA suppliers need a good bitch slapping over their tools plus their sales depts need to indulge in slightly less masturbatory congratulations about how wonderful their latest retro 80’s tool sets are.
I have been using Altera for some time.I thought it is more user friendly and they offer a lot of different development boards also. I have used Xilinx in the past and found little difficult, may be because I was new to FPGA at that time.
Altera had a built in simulator in version 9.1 but they changed it to modelsim after v9.1. It was a bit frustrating for me to learn the new simulator at last I gave up and I stopped upgrading the version.
Nice review and informative. I will definitely try out Xilinx FPGA platform.
Could you suggest the best starter board for Xilinx?
If you don’t need I/Os and are just interested into the FPGA itself, the Avnet Spartan-6 LX9 MicroBoard is cheap at $89.
If you need I/Os, LAN & VGA, I would opt for a Digilent Nexys 3 board at $199.
But if you need high-speed differential I/Os, I would definitively recommend the Avnet Spartan-6 LX16 Evaluation Kit at $225 for its LPC FMC expansion header.
Here is a nice list:
http://tristesse.org/CheapFPGADevelopmentBoards
It’s funny you should mention that wrapper GUI Steve, as that is basically what the Altium Designer suite does (it also does a myriad of other things including PCB design, electronics circuit simulation, embedded programming etc. as long as you have the license for it). It allows for high level FPGA development without having to worry about which brand you are using. I once obtained one of their dev kits (NB3000) which I was very excited about at the time, but I have a handful of issues with it:
-the Altium interface assaults you with more options and buttons than you can look at
-every second time I make a new project I can’t compile it due to some obscure error (indeed, it’s all so high-level that I don’t even know where to start looking)
-in order to compile a project the vendor tools need to be installed (i.e., Altium = 5.2GB + Xilinx ISE = 10GB), and if the compilation stalls due to an error, I am again clueless as to the source
-Though the initial kit is ‘affordable’ at $400, you need to get a new license every year, which would scare away any hobbyist
In short, it’s a high level tool that requires low level knowledge with too many bugs to make it ‘pro’ but too expensive for a hobbyist. But in the occasions that you do get it working, it’s amazing!
We use Altera, and are also sad that the simulator dissapeared after 9.1. We also make extensive use of block diagrams at the higher levels to connect modules, see the flow, and visually understand the whole design. Being a visual person I would find this hard to live without. I cannot find a similar method of design entry in ISE. Can anyone tell me if block diagramming (as a design entry tool) is available in ISE?
Thanks.
Bart: Yes, ISE has a schematic capture mode. See: http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20WebPACK%20Schematic%20Capture%20Tutorial.pdf
I just installed the Altera Web edition and tried a gate-level simulation to be greeted with “Unresolved Defparam Refrences”.
Debugged for quite a while then commented out the “Defparam”, in the test.vo(Verilog) file, the Simlulator said that “Only single HDL is supported”, so I figured the Cyclone libraries were VHDL as you said above.
Might try the .INI file modification or in VHDL. Justed really wanted to know what was going on?
I am surprised there are so few references to this issue out there.
For last three years I have been working with xilinx. It was very difficult to learn from scratch. I am still not a master my any means but I know enough to get the job done. Recently I lost my job, so the comapany laptop. I tried to install xilinx free ise webpack on my home laptop. xilinx was keep asking for coporate e-mail that i don’t have anymore. So what to do with corporate e-mail? The answer is nothing I could do. I tried many different things but finally I said screw it and started to look at Altera. BIG difference, easy to use softwares and tutorials helped me out with a quick boost. I am sure I will spend considerable time to learn Altera environment but it seems worth it. Thanks Altera, I am glad to use your product.
(circa oct2013)
The real problem, I think, hobbyist face with Xilinx and Altera is dealing with IP and the tool costs that are in addition to the development kit hardware.
For example: $500 for the altera/xilinx kit hardware and then potentially hundreds/thousands more for soft-core processors/IP and the development environment after that… Plus the joy of debugging/optimizing HW while you write the SW… The alternative is a TI DSP with 8 cores @1.2GHz, RTOS, and plenty of RAM…and no additional IP costs/concerns–Why would a hobbyist bother with the FPGA?
As a hobby-level user, it is very risky to waste time learning how to use tools, then implementing a design, and then finding out I have to stay tethered to my laptop/desktop for it to ‘run’ or that it won’t work unless I upgrade my SW toolset. Even with a license or machine that I could borrow from work, the DSP/MCU path makes a lot more sense… especially w.r.t controlling MY IP distribution!
While I have my gripes about the tools, I don’t really see the issues you mentioned as problems for hobbyists. What you’ve described sounds more like the experience with very high-end FPGAs and their tools. Entry-level kit hardware is $100-$200, not $500. Or as little as $15 for a CPLD demo board. The development software is free. There are plenty of free soft-core processors (e.g. OpenCores), or create your own design like I did. There’s no requirement to stay tethered to a computer in order for your design to run. A high-speed DSP or MCU is a great tool for many tasks, but doesn’t let you experiment with CPU design if that was your goal, and isn’t any help if you’re designing something non-CPU-like.
Thanks for the reply!
I think I did a really poor job explaining that, to me, projects generally require them to be w/o a host machine to monitor/help them and those are generally ‘non-CPU-like’ tasks–as you pointed out. And while they may or may not include a CPU in the design, it is just part of the architecture, not the purpose of the exercises. You described a couple of tasks/situations that didn’t occur to me.
I would like to say:
Cyclone-IV boards are available for less than $100, and the ($80)DE0-Nano with integrated USBJTAG and powered from USB would be a good platform to explore CPU single and multi-core design. It is an entry-level platform by a lot of definitions… but still has ram/flash, an ADC, an accelerometer, and some LEDs–plus tons of GPIO/LVDS and room.
The tools are really the point though. There is Hobby-priced, very-capable hardware out there that I want to use but the Hobby-grade tools are so-very-crippled (for what I want to do). I doubt that Altera/Xilinx make enough off licensing fees that they sell the chips at a loss… It really frustrates me, and pushes me off into DSP-MCU-land that has un-crippled tools, but really pitiful HW considering what is possible!
Thanks for the articles!
I’ve used Xilinx professionally for about 40 years (about the age of the company). Both companies are caught in a bad catch 22. The product (FPGA) is ideally suited to hobbyists, prototypes and short run manufacturing, because of its programability and flexibility. However the tools are extremely complex. They have to do translation for schematic/HDL to the lower level that the IC actually supports. They have to do placement and routing. Then there is optimization, which is huge. Not to mention simulation and timing closure. A huge amount of development goes into the tools. Similarly complex tools for ASICs cost around 100K!
Then there are the real kickers: Hobbyists, and short run manufacturing don’t buy enough instances of the ICs to support a company, let alone the tool development. But high volume customers are probably going to want to go to ASIC, because it is cheaper and can achieve a higher level of integration (things like mixed signal). So their financial survival depends on a sweet spot in the middle, large enough volume to pay the bills but not so large as to go to ASIC.
And the final kicker–support. The smaller the volume a customer does, the more support they are going to need, because they are more likely to be new to the ideas, less experienced and trained, and use the tools infrequently enough to forget things. Larger customers will only need support with serious bugs or things that are pushing the limits of the technology.
My biggest complain is that Xilinx basically won’t talk to you unless you do $250M annual business with them. I don’t know how Altera does. But that is the biggest show stopper for me. I’m a professional developer, although all of my clients are small quantity products and I also cover a wide cross-section of the industry, so FPGAs are a small percentage of what I do. The questions I raise are almost always legitimate bugs in the tools, yet I can’t get answers. I bang my head against a wall for weeks or months until I discover a work around for myself or give up. They just don’t care! I’m too small of a blip on their financial picture to even waste a few hundred dollars in technical support. I don’t think I can even buy support.
I understand their problem. They have to be profitable. But they are in a difficult situation. The customers who are most likely to make them profitable are the ones that need them the least and are most likely to abandon ship for ASIC. The customers that need them the most, that perfectly fit the model of the product they sell, least fit the business model they need to succeed.
Hello,
Thanks for the head-to-head comparison.
I have a IR receiver home project that I would like to build for receiving multiple audio channels and demodulate/decode and play a channel. Data rates just under 1Mbps, with signal processing blocks such as PSK Demod, Synchronization, Reed-Solomon decoder etc.
Looks like I need an FPGA.
Was wondering if there are any recommendations on choice of platform???? Appreciate the input.
Some criteria that came to mind that may not be covered above are: IP Blocks available, easy of using them, ease of use/debug and cost of SW and FPGA for someone who probably just needs 1 or 2 units.
I am leaning more towards embedded solution but a starter kit would probably be OK to begin with. I have had some experience with Xilinx ISE for running synthesis, Modelsim simulation, and downloading via JTAG, but that was 10 years ago.
Thank You.
Thanks for the insights, got some real feeling about the differences. since i know xilinx simulation and programming(ISE) its good to know that xilinx simulation goes well into real design.
Am I the only person that has a problem with their Xilinx “IP” junk emitting 800 warnings about unused, inaccessible memory controller ports and AXI? I use one of the Spartan6 integrated memory controllers in 128-bit mode, so it merges all the ports into one big 128-bit load and store port. Due to that I am only using port 0, not using port 1 thru 5 (they don’t work in 128 bit mode). Now the build emits hundreds of warnings. I am using their native interface too, not AXI, all their AXI interface bus stuff generates hundreds of warnings. Their IP wizard generated garbage code leaves hundreds of connections unconnected. I wonder what their toolchain build itself looks like, apparently tens of thousands of warnings if their verilog compiler is any indication. I can’t turn off those warnings either, I NEED those warnings on my stuff. I have to wade through a wall of useless warnings in the IP, every build.