An explanation of the components shown on the block diagram I posted yesterday.

Registers:

• A is the accumulator register, although the hardware assigns it no special significance, and X can do anything that A can.
• X is the index register. It can be used for indexed addressing modes, where the value in X specifies an offset from a base address to get the effective address. It can also be used as a general-purpose register.
• T is a temporary register, used by the microcode to implement various instructions, but not visible to the application programmer.
• The pseudo-register X7 is used to sign-extend the 8-bit value of X when adding it to a 16-bit address.
• 0 is just a hard-wired 0 value.
• CC is the condition code register, which stores the flags (equal, carry, etc) from an ALU operation. It’s a parallel in, serial out shift register, so only one flag can be examined per clock cycle, and it may be necessary to spend a few cycles to shift the desired flag into position to be read. I stole this design from my college textbook.

Addressing: Any of three different sources can be selected by the microcode to drive the address bus on a given clock cycle. The low or high byte of the address bus can also drive the data bus if needed. The address registers are counters, and so can be incremented or decremented without using the ALU. None of the address registers are directly visible to the application programmer.

• PC is the 16-bit program counter, with separate low and high bytes.
• SP is the 16-bit stack pointer.
• AR is a generic 16-bit address register, used for memory accesses where the value in PC and SP can’t be disturbed.

Control: The microcode is stored in 3 parallel 8K ROMs, yielding 13 inputs and 24 outputs. The inputs are the opcode register OP for the current instruction (8 bits), the phase (a 4-bit counter, essentially a PC for the microcode), and the flag input from the condition code register. The outputs are:

• ALU left input selection: 2 bits
• ALU right input selection: 2 bits
• ALU function (add, subtract, shift, etc): 6 bits
• ALU drive enable: 1 bit
• Data load enable signals (can be one of A, X, T, PCLO, PCHI, ARLO, ARHI, MEMORY): 3 bits
• Enable CC: 1 bit
• Load/~Shift CC: 1 bit
• Address bus source (can be one of PC, AR, SP): 2 bits
• AR++: 1 bit
• PC++: 1 bit
• SP++: 1 bit
• SP–: 1 bit
• OP load enable: 1 bit
• Not connected: 1 bit

A microcde example might help.

ADC (Add With Carry): Interpret the next 2 bytes after the opcode as a memory address, read a value from that address, and add it to the accumulator, loading the CC register with the carry flag. 4 clock cycles.

Memory: I expect to have RAM, ROM, a combination UART/USB interface, and console switches share a single 64K address space. I plan to use a single-chip USB interface solution like this one, which should be easier than a serial port for connecting to a PC. I haven’t yet looked at it in detail, though. The exact type of ROM (EPROM, E/EPROM, Flash) is still up in the air as well.